1. Field of the Invention
The present invention relates to a semiconductor device, especially, the structure of a semiconductor device comprising a capacitor.
2. Description of the Background Art
FIG. 39 is a cross-sectional view showing the structure of a conventional capacitor used in LSI. On a semiconductor substrate 101, there is formed an insulation film 120 on which an insulation film 103 and a capacitor comprising a pair of polysilicon films 102, 104 sandwiching the insulation film 103 are formed. An interlayer insulation film 105 is formed on the capacitor, and metal wires 106, 107 are selectively formed on the interlayer insulation film 105. The metal wires 106, 107 are electrically connected to the polysilicon films 102, 104 through contact holes 108, 109 formed in the interlayer insulation film 105, respectively.
FIG. 40 is a cross-sectional view showing the structure of another conventional capacitor. An interlayer insulation film 112 and a capacitor comprising metal wires 110, 111 facing across the interlayer insulation film 112 are formed on the insulation film 120.
In the conventional capacitor in FIG. 39, the polysilicon films 102 and 104 have high parasitic resistance, so its equivalent circuit is as shown in FIG. 41. High power losses due to parasitic resistance R101, R102 make the capacitor useless for an analog circuit.
In the capacitor in FIG. 40, on the other hand, the use of the metal wires 110, 111 allows the capacitor to have low parasitic resistance and low power losses. However, since the interlayer insulation film 112 is thick (about 1 xcexcm for a device using 0.2-xcexcm design rules), a large area is necessary to obtain a high-capacitance capacitor.
A first aspect of the present invention is directed to a semiconductor device comprising: an underlying layer having a main surface; and a capacitor formed on the main surface of the underlying layer. The capacitor has at least one line and space structure in which a plurality of metal wires each extending in a first direction of the main surface are electrically isolated from each other by an insulation film and aligned in a second direction of the main surface perpendicular to the first direction.
According to a second aspect of the present invention, in the semiconductor device of the first aspect, the line and space structure includes a first wire serving as one electrode and a second wire serving as the other electrode, the first wire and the second wire being aligned alternately.
According to a third aspect of the present invention, in the semiconductor device of the second aspect, the capacitor further includes at least one flat electrode which is parallel to the main surface and aligned with the line and space structure in a third direction perpendicular to the main surface through a predetermined interlayer insulation film.
According to a fourth aspect of the present invention, in the semiconductor device of the second aspect, the at least one line and space structure includes three or more line and space structures. The three or more line and space structures are stacked in layers with an interlayer insulation film interposed therebetween so that the first wire and the second wire in different ones of the line and space structures are aligned alternately in a third direction perpendicular to the main surface.
According to a fifth aspect of the present invention, in the semiconductor device of the fourth aspect, the capacitor further includes at least one flat electrode which is parallel to the main surface and aligned with the line and space structures in the third direction through a predetermined interlayer insulation film.
According to a sixth aspect of the present invention, in the semiconductor device of the second aspect, the at least one line and space structure includes a plurality of line and space structures. The plurality of line and space structures are stacked in layers with an interlayer insulation film interposed therebetween so that the first wires in different ones of the line and space structures are aligned and the second wires in different ones of the line and space structures are aligned, in a third direction perpendicular to the main surface. The first wires and the second wires aligned in the third direction are electrically connected to each other by through holes which are filled with conductors and formed in the interlayer insulation film.
According to a seventh aspect of the present invention, in the semiconductor device of the sixth aspect, the capacitor further includes at least one flat electrode which is parallel to the main surface and aligned with the line and space structures in the third direction through a predetermined interlayer insulation film.
According to an eighth aspect of the present invention, in the semiconductor device of either of the three, fifth, and seventh aspects, the at least one flat electrode includes a plurality of flat electrodes which are arranged on both sides of the line and space structures in alignment with the line and space structures in the third direction.
According to a ninth aspect of the present invention, in the semiconductor device of either of the three, fifth, seventh, and eighth aspects, the capacitor further includes a through hole which is filled with a conductor and formed in the predetermined interlayer insulation film to provide an electrical connection between the first wire and the flat electrode.
According to a tenth aspect of the present invention, in the semiconductor device of the seventh aspect, the capacitor further includes: a first through hole which is filled with a conductor and formed in the predetermined interlayer insulation film to provide an electrical connection between the first wire and the flat electrode; another flat electrode which is arranged outside the flat electrode through another interlayer insulation film in alignment with the line and space structures in the third direction on the same side as the flat electrode; and a second through hole which is filled with a conductor and formed in the another interlayer insulation film to provide an electrical connection between the second wire and the another flat electrode.
According to an eleventh aspect of the present invention, in the semiconductor device of the first aspect, the capacitor further includes: an interlayer insulation film formed on the line and space structure; and a highly dielectric film which is formed in contact part between the interlayer insulation film and the line and space structure and has a higher dielectric constant than a silicon oxide film.
According to a twelfth aspect of the present invention, in the semiconductor device of the first aspect, the insulation film is a highly dielectric film which has a higher dielectric constant than a silicon oxide film.
According to a thirteenth aspect of the present invention, in the semiconductor device of either of the eleventh and twelfth aspects, the semiconductor device has a wiring portion in which desired wires are formed and a capacitor portion in which the capacitor is formed; and the highly dielectric film is provided only in the capacitor portion.
According to a fourteenth aspect of the present invention, in the semiconductor device of either of the eleventh and twelfth aspects, the semiconductor device has a wiring portion in which desired wires are formed and a capacitor portion in which the capacitor is formed; and the insulation film in the wiring portion is a silicon oxide film doped with impurities for reducing the dielectric constant.
According to a fifteenth aspect of the present invention, in the semiconductor device of either of the first to fourteenth aspects, both line and space widths of the line and space structure are not more than 0.2 xcexcm.
The semiconductor device of the first aspect adopts metal wires of low resistance as the wires in the line and space structure and utilizes capacitances between adjacent metal wires to form a capacitor. Accordingly, a small-sized high-capacitance capacitor with low parasitic resistance and low power losses can be obtained.
In the semiconductor device of the second aspect, the first wire and the second wire are aligned alternately. This simplifies the formation of a high-capacitance capacitor.
The semiconductor device of the third aspect forms capacitances between the first or second wire and the flat electrode. This allows a further increase in capacity.
Further, low power loss allows the formation of a desirable capacitor with no parasitic components, and the presence of the flat electrode reduces interference between the first or second wire and other signal lines.
In the semiconductor device of the fourth aspect, the first and second wires form capacitances between adjacent four of the second and first wires which are aligned in the second and third directions. This allows a further increase in capacity.
The semiconductor device of the fifth aspect forms capacitances between the first or second wire and the flat electrode. This allows a further increase in capacity.
Further, low power loss allows the formation of a desirable capacitor with no parasitic components, and the presence of the flat electrode reduces interference between the first or second wire and other signal lines.
The semiconductor device of the sixth aspect forms capacitances between adjacent through holes sandwiching the interlayer insulation film. This allows a further increase in capacity.
The semiconductor device of the seventh aspect forms capacitances between the first or second wire and the flat electrode. This allows a further increase in capacity.
Further, low power loss allows the formation of a desirable capacitor with no parasitic components, and the presence of the flat electrode reduces interference between the first or second wire and other signal lines.
In the semiconductor device of the eighth aspect, a plurality of flat electrodes are provided on both sides of the line and space structure. This enhances the effects of the third, fifth, and seventh aspects.
In the semiconductor device of the ninth aspect, the second wire is surrounded by the first wire, the flat electrode, and the through hole which provides an electrical connection between the first wire and the flat electrode. This effectively reduces interference between the second wire and other signal lines.
Further, the capacitance formed between the second wire and the through hole which provides an electrical connection between the first wire and the flat electrode allows a further increase in capacity.
In the semiconductor device of the tenth aspect, the first wire, the flat electrode, the first through hole, and the through hole which provides an electrical connection between the first wires are surrounded by the second wire, another flat electrode, the second through hole, and the through hole which provides an electrical connection between the second wires. This effectively reduces interference between the first wire and other signal lines.
The semiconductor device of the eleventh aspect allows an increase in capacity as compared with the case where the insulation film is composed only of a silicon oxide film.
The semiconductor device of the twelfth aspect allows an increase in capacity as compared with the case where the insulation film is composed only of a silicon oxide film.
The semiconductor device of the thirteenth aspect achieves an increase in capacity in the capacitor portion and low parasitic capacitance and high-speed operation in the wiring portion.
The semiconductor device of the fourteenth aspect reduces parasitic capacitance in the wiring portion, thus achieving high-speed operation.
The semiconductor device of the fifteenth aspect allows an increase of about one order of magnitude in capacity per unit area as compared to the case where the capacitor is composed of flat electrodes.
An object of the present invention is to provide a small-sized low-power-loss capacitor.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.